Field effect transistors (FETs) are the basic building block of today's integrated circuits. Such transistors can be formed in conventional bulk substrates (such as silicon) or in semiconductor-on-insulator (SOI) substrates.
State of the art FETs are fabricated by depositing a gate electrode over a gate dielectric and a substrate. Generally, the transistor fabrication process implements lithography and etching processes to define the conductive, e.g., polysilicon, gate structures. The gate structure and substrate are then typically, but not necessarily always, thermally oxidized, and, after this, source/drain extensions are formed by implantation. Sometimes the implant is performed using a source/drain extension spacer to create a specific distance between the gate and the implanted junction. In some instances, such as in the manufacture of an n-FET device, the source/drain extensions for the n-FET device are implanted with no source/drain extension spacer. For a p-FET device, the source/drain extensions are typically implanted with a source/drain extension spacer present. A thicker spacer than the source/drain extension spacer is typically formed after the source/drain extensions have been implanted. The deep source/drain implants are then performed with the thick spacer present. High temperature anneals are performed to activate the junctions after which the source/drain and top portion of the gate are generally silicided. Silicide formation typically requires that a refractory metal be deposited on a Si-containing substrate followed by a high temperature thermal anneal process to produce the silicide material. The silicide process forms low resistivity contacts to the deep source/drain regions and the gate conductor.
In the above, the thicker spacer provides self-aligned offset between the gate electrode (i.e., polysilicon or any other conductive material) and the implanted dopants which are used to tailor the semiconductor electrical characteristics of the FET.
In order make integrated circuits (ICs), such as memory, logic and other devices of higher integration than currently feasible one has to find a way to further downscale the dimensions of FETs. The downscaling of transistor dimensions allows for improved performance as well as compactness, but such downscaling has some device degrading effects. Generational improvements for high performance FET devices are obtained by decreasing the transistor line width, reducing the gate oxide thickness, and decreasing the source/drain extension resistance. Smaller transistor line width results in less distance between the source and the drain. This results in faster switching speeds for complementary metal oxide semiconductor (CMOS) circuits.
In addition to the above, the spacers used with the downscaled FET must also be downscaled accordingly in order to provide compact devices. However, conventional methods of forming a spacer which include deposition of a dielectric material, such as an oxide of silicon or a nitride of silicon, and anisotropic etching are becoming less practical as the scaling of the devices continues. The anisotropic etching step used in spacer formation is also undesirable since it typically modifies, removes and/or damages the various materials that are within the field of the FET.
It is noted that the above problems are not only related to FET devices. Instead, the aforementioned problems with conventional spacer formation and device scaling are present with any nanostructure which includes a spacer that abuts a topographic edge of a material or material stack present within the structure.
In view of the above, there is a need for providing new and improved spacers that can be used in various nanostructures to protect a topographic edge of a material or material stack present within the structure. In particular, a new and improved spacer is needed for protecting an edge of a gate stack structure.